Multilevel metal interconnect structures are routinely employed to provide electrical wiring for a high density circuitry, such as semiconductor devices on a substrate. Continuous scaling of semiconductor devices leads to a higher wiring density as well as an increase in the number of wiring levels. For example, a 3D NAND stacked memory device may include many levels of control gate electrically conductive layers. Contact via structures extending through many wiring levels can generate significant stress due to the volume of a stress-generating material in the contact via structures.